 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| 1 features ? conservative and repeatable measurement of available charge in rechargeable batteries ? designed for portable equipment such as power tools with high dis - charge rates ? designed for battery pack inte - gration - 120 a typical standby current (self-discharge estimation mode) - small size enables imple- mentations in as little as 1 2 square inch of pcb ? direct drive of leds for capacity display ? self-discharge compensation us- ing internal temperature sensor ? simple single-wire serial commu- nications port for subassembly testing ? 16-pin narrow soic general description the bq2011k gas gauge ic is in - tended for battery-pack installation to maintain an accurate record of a bat - tery?s available charge. the ic moni - tors a voltage drop across a sense re - sistor connected in series between the negative battery terminal and ground to determine charge and discharge ac - tivity of the battery. the bq2011k is designed for systems such as power tools with very high discharge rates. battery self-discharge is estimated based on an internal timer and tem - perature sensor. compensations for battery temperature and rate of charge or discharge are applied to the charge, discharge, and selfdischarge calculations to provide available charge information across a wide range of operating conditions. initial battery capacity is set using the prog 1-4 and spfc pins. actual battery capacity is automatically ?learned? in the course of a dis- charge cycle from full to empty and may be displayed depending on the display mode. nominal available charge may be di - rectly indicated using a five-seg - ment led display. these segments are used to graphically indicate nominal available charge. the bq2011k supports a simple single-line bidirectional serial link to an external processor (common ground). the bq2011k outputs bat - tery informa tion in response to exter - nal commands over the serial link. to support sub assembly testing, the outputs may also be controlled by command. the external processor may also overwrite some of the bq2011k gas gauge data registers. the bq2011k may operate directly from four cells. with the ref out- put and an external transistor, a simple, inexpensive regulator can be built to provide v cc from a greater number of cells. internal registers include available charge, temperature, capacity, battery id, and battery status. lcom led common output seg 1 /prog 1 led segment 1/ program 1 input seg 2 /prog 2 led segmen t 2 / program 2 input seg 3 /prog 3 led segment 3/ program 3 input seg 4 /prog 4 led segment 4/ program 4 input seg 5 led segment 5 spfc programmed full count selection input ref voltage reference output nc no connect dq serial communications input/output rbi register backup input sb battery sense input disp display control input sr sense resistor input v cc 3.0?6.5v v ss negative battery terminal gas gauge ic for high discharge rates bq2011k 10/97 b pin connections pin names 1 pn2011jk.eps 16-pin narrow soic 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 v cc ref nc dq rbi sb disp sr lcom seg 1 /prog 1 seg 2 /prog 2 seg 3 /prog 3 seg 4 /prog 4 seg 5 spfc v ss
pin descriptions lcom led common open-drain output switches v cc to source cur - rent for the leds. the switch is off during ini - tialization to allow reading of prog 1-4 pull-up or pull-down program resistors. lcom is high impedance when the display is off. seg 1 ? seg 5 led display segment outputs each output may activate an led to sink the current sourced from lcom, the battery, or v cc . prog 1 ? prog 4 programmed full count selection inputs (dual function with seg 1 - seg 4 ) these three-level input pins define the pro - grammed full count (pfc) in conjunction with spfc pin, define the display mode and enable or disable self-discharge. spfc programmed full count selection input this three-level input pin along with prog 1-3 define the programmed full count (pfc) thresholds described in table 1. the state of the spfc pin is only read immediately after a reset condition. sr sense resistor input the voltage drop (v sr ) across the sense re- sistor r s is monitored and integrated over time to interpret charge and discharge activ - ity. the sr input is tied to the low side of the sense resistor and battery pack ground (see figure 1). v sr >v ss indicates discharge, and v sr ternal bq2011k registers when v cc momentarily drops be - low 3.0v. v cc is output on rbi when v cc is above 3.0v. after v cc rises above 3.0v, the bq2011k checks the internal registers for data loss or corruption. if data has changed, then the nac register is cleared, and the lmd register is loaded with the initial pfc. voltage thresholds in conjunction with monitoring v sr for charge/discharge currents, the bq2011k monitors the single-cell battery po - tential through the sb pin. the single-cell voltage poten - tial is determined through a resistor-divider network per the following equation: rb rb n 1 2 1 =? where n is the number of cells, rb 1 is connected to the positive battery terminal, and rb 2 is connected to the negative battery terminal. the single-cell battery volt - age is monitored for the end-of-discharge voltage (edv) and for maximum cell voltage (mcv). the edv thresh - old level is used to determine when the battery has reached an ?empty? state, and the mcv threshold is used for fault detection during charging. the mcv threshold for the bq2011k is fixed at: v mcv = 2.00v the edv threshold varies as a function of discharge cur- rent as follows: reset reset can be accomplished with a command over the se - rial port as described on page 13. temperature the bq2011k internally determines the temperature in 10c steps centered from -35c to +85c. the tempera - ture steps are used to adapt charge and discharge rate compensations, self-discharge counting, and available charge display translation. the temperature range is available over the serial port in 10c increments as shown below: layout considerations the bq2011k measures the voltage differential between the sr and v ss pins. v os (the offset voltage at the sr pin) is greatly affected by pc board layout. for optimal results, the pc board layout should follow the strict rule of a single-point ground return. sharing high-current ground with small signal ground causes undesirable noise on the small signal nodes. additionally: the capacitors (sb and v cc ) should be placed as close as possible to the sb and v cc pins, respectively, and their paths to v ss should be as short as possible. a high-quality ceramic capacitor of 0.1 f is recommended for v cc . the sense resistor (r s ) should be as close as possible to the bq2011k. the r-c on the sr pin should be located as close as possible to the sr pin. the maximum r should not exceed 20k. gas gauge operation the operational overview diagram in figure 2 illus - trates the operation of the bq2011k. the bq2011k accu - mulates a measure of charge and discharge currents, as well as an estimation of self-discharge. charge currents are temperature and rate compensated, whereas self- discharge is only temperature compensated. the main counter, nominal available charge (nac), represents the available battery capacity at any given time. battery charging increments the nac register, while battery discharging and self-discharge decrement 4 bq2011k tmpgg (hex) temperature range 0x < -30c 1x -30c to -20c 2x -20c to -10c 3x -10c to 0c 4x 0c to 10c 5x 10c to 20c 6x 20c to 30c 7x 30c to 40c 8x 40c to 50c 9x 50c to 60c ax 60c to 70c bx 70c to 80c cx > 80c v sro (mv) v edv (v) 010 < v sro 1.160 10 20 < v sro 1.124 20 40 < v sro 1.060 40 60 < v sro 0.960 v sro > 60 0 (ovld) the nac register and increment the dcr (discharge count register). the discharge count register (dcr) is used to update the last measured discharge (lmd) register only if a complete battery discharge from full to empty occurs without any partial battery charges. therefore, the bq2011k adapts its capacity determination based on the actual conditions of discharge. the battery?s initial capacity is equal to the pro - grammed full count (pfc) shown in table 1. until lmd is updated, nac counts up to but not beyond this threshold during subsequent charges. this approach al - lows the gas gauge to be charger-independent and com - patible with any type of charge regime. 1. last measured discharge (lmd) or learned battery capacity: lmd is the last measured discharge capacity of the battery. on initialization (application of v cc or bat - tery replacement), lmd = pfc. during subsequent discharges, the lmd is updated with the latest measured capacity in the discharge count register (dcr) representing a discharge from full to below edv. a qualified discharge is necessary for a ca- pacity transfer from the dcr to the lmd register. the lmd also serves as the 100% reference thresh- old used by the relative display mode. 2. programmed full count (pfc) or initial bat - tery capacity: the initial lmd and gas gauge rate values are pro - grammed by using pfc. the pfc also provides the 100% reference for the absolute display mode. the bq2011k is configured for a given application by se - lecting a pfc value from table 1. the correct pfc may be determined by multiplying the rated bat - tery capacity in mah by the sense resistor value: battery capacity (mah) * sense resistor ( ? ) = pfc (mvh) selecting a pfc slightly less than the rated capac - ity for absolute mode provides capacity above the full reference for much of the battery?s life. example: selecting a pfc value given: sense resistor = 0.002 ? number of cells = 6 capacity = 1800mah, nicd cells current range = 1a to 80a absolute display mode self-discharge = c 80 voltage drop across sense resistor = 2mv to 160mv 5 bq2011k fg201104.eps temperature compensation charge current discharge current self-discharge timer temperature translation nominal available charge (nac) last measured discharged (lmd) discharge count register (dcr) < qualified transfer + rate and temperature compensation rate and temperature compensation temperature step, other data + - inputs main counters and capacity reference (lmd) outputs serial port chip-controlled available charge led display - + figure 2. operational overview therefore: 1800mah * 0.002 ? = 3.6mvh select: pfc = 35840 counts or 3.39mvh spfc = z (float) prog1, prog 2=horz prog3 = l prog 4=horz the initial full battery capacity is 3.39mvh (1695mah) un - til the bq2011k ?learns? a new capacity with a qualified discharge from full to edv. 3. nominal available charge (nac): nac counts up during charge to a maximum value of lmd and down during discharge and self dis - charge to 0. nac is reset to 0 on initialization and on the first valid charge following discharge to edv. to prevent overstatement of charge during periods of overcharge, nac stops incrementing when nac = lmd. note: nac is set to the value in lmd when prog 4 is pulled low during a reset. 6 bq2011k programmed full count (pfc) mvh scale display mode spfc prog 1 prog 2 prog 3 40192 3.81 1 10560 absolute h h or z h or z h or z 32256 3.05 1 10560 z h or z h or z h or z 28928 2.74 1 10560 l h or z h or z h or z 25856 2.45 1 10560 h l h or z h or z 35840 3.39 1 10560 z l h or z h or z 23296 2.21 1 10560 l l h or z h or z table 1. bq2011k programmed full count mvh selections prog 4 nac reset value self-discharge h or z nac = 0 enabled l nac = pfc disabled table 2. programmed self-discharge 4. discharge count register (dcr): the dcr counts up during discharge independent of nac and could continue increasing after nac has decremented to 0. prior to nac = 0 (empty battery), both discharge and self-discharge incre - ment the dcr. after nac = 0, only discharge in - crements the dcr. the dcr resets to 0 when nac = lmd. the dcr does not roll over but stops counting when it reaches ffffh. the dcr value becomes the new lmd value on the first charge after a valid discharge to v edv if: no valid charge initiations (charges greater than 256 nac counts; or 0.006 ? 0.01c) occurred during the period between nac = lmd and edv detected. the self-discharge count is not more than 4096 counts (8% to 18% of pfc, specific percentage threshold determined by pfc). the temperature is 0c when the edv level is reached during discharge. the valid discharge flag (vdq) indicates whether the present discharge is valid for lmd update. charge counting charge activity is detected based on a negative voltage on the v sr input. if charge activity is detected, the bq2011k increments nac at a rate proportional to v sro (v sr +v os ) and, if enabled, activates an led display if v sro < -2mv. charge actions increment the nac af- ter compensation for charge rate and temperature. the bq2011k determines a valid charge activity sus - tained at a continuous rate equivalent to v sro < -400 v. a valid charge equates to a sustained charge activity greater than 256 nac counts. once a valid c harge is de - tected, charge counting continues until v sro rises above -400 v. discharge counting all discharge counts where v sro > 500 v cause the nac register to decrement and the dcr to increment. exceeding the fast discharge threshold (fdq) if the rate is equivalent to v sro > 2mv activates the display, if en - abled. the display remains active for 10 seconds after v sro falls below 2mv. self-discharge estimation the bq2011k continuously decrements nac and incre - ments dcr for self-discharge based on time and tem - perature. the self-discharge count rate is programmed to be a nominal 1 80 * nac rate per day or disabled per table 2. this is the rate for a battery temperature be - tween 20?30c. the nac register cannot not be decre - mented below 0. count compensations the bq2011k determines fast charge when the nac up - dates at a rate of 2 counts/sec. charge activity is com - pensated for temperature and rate before updating the nac and/or dcr. self-discharge estimation is compen - sated for temperature before updating the nac or dcr. charge compensation two charge efficiency factors are used for trickle charge and fast charge. fast charge is defined as a rate of charge resulting in 2 nac counts/sec ( 0.15c to 0.32c depending on pfc selections; see table 1). the compen- sation defaults to the fast charge factor until the actual charge rate is determined. temperature adapts the charge rate compensation fac- tors over three ranges between nominal, warm, and hot temperatures. the compensation factors are shown below. discharge compensation corrections for the rate of discharge are made by adjust - ing edv thresholds. the compensation factor used dur - ing discharge is set to 1.00 for all rates and tempera - tures. the recoverable charge at colder temperatures is adjusted for display purposes only. see page 13. 7 bq2011k charge temperature trickle charge compensation fast charge compensation <30c 0.80 0.95 30?50c 0.75 0.90 > 50c 0.70 0.85 self-discharge compensation the self-discharge compensation is programmed for a nominal rate of 1 80 * nac per day or disabled. this is the rate for a battery within the 20?30c temperature range (tmpgg = 6x). this rate varies across 8 ranges from <10c to >70c, doubling with each higher tem - perature step (10c). see table 3. error summary the lmd is susceptible to error on initialization or if no updates occur. on initialization, the lmd value in- cludes the error between the programmed full capacity and the actual capacity. this error is present until a valid discharge occurs and lmd is updated (see the dcr description in the ?layout considerations? section). the other cause of lmd error is battery wear-out. as the battery ages, the measured capacity must be ad - justed to account for changes in actual battery capacity. current-sensing error table 4 illustrates the current-sensing error as a func - tion of v sr . a digital filter eliminates charge and discharge counts to the nac register when v sro (v sr + v os ) is between -400 v and 500 v. communicating with the bq2011k the bq2011k includes a simple single-pin (dq plus re - turn) serial data interface. a host processor uses the in - terface to access various bq2011k registers. battery char - acteristics may be easily monitored by adding a single con - tact to the battery pack. the open-drain dq pin on the bq2011k should be pulled up by the host system, or may be left floating if the serial interface is not used. the interface uses a command-based protocol, where the host processor sends a command byte to the bq2011k. the command directs the bq2011k to either store the next eight bits of data received to a register specified by the command byte or output the eight bits of data speci - fied by the command byte. the communication protocol is asynchronous return-to- one. command and data bytes consist of a stream of eight bits that have a maximum transmission rate of 333 bits/sec. the least-significant bit of a command or data byte is transmitted first. the protocol is simple enough that it can be implemented by most host processors using either polled or interrupt processing. data input from the bq2011k may be sampled using the pulse-width capture timers available on some microcontrollers. communication is normally initiated by the host proces- sor sending a break command to the bq2011k. a break is detected when the dq pin is driven to a logic-low state for a time, t b or greater. the dq pin should then be returned to its normal ready-high logic state for a time, t br . the bq2011k is now ready to re - ceive a command from the host processor. the return-to-one data bit frame consists of three distinct sections. the first section is used to start the transmission by either the host or the bq2011k taking the dq pin to a 8 bq2011k temperature range self-discharge compensation typical rate/day < 10c nac 320 10?20c nac 160 20?30c nac 80 30?40c nac 40 40?50c nac 20 50?60c nac 10 60?70c nac 5 > 70c nac 25 . table 3. self-discharge compensation symbol parameter typical maximum units notes inl integrated non-linearity error 2 4 % add 0.1% per c above or below 25c and 1% per volt above or below 4.25v. inr integrated non- repeatability error 1 2 % measurement repeatability given similar operating conditions. table 4. bq2011k current-sensing errors logic-low state for a period, t strh,b . the next section is the actual data transmission, where the data should be valid by a period, t dsu , after the negative edge used to start commu - nication. the data should be held for a period, t dv , to allow the host or bq2011k to sample the data bit. the final section is used to stop the transmission by return - ing the dq pin to a logic-high state by at least a period, t ssu , after the negative edge used to start communication. the final logic-high state should be held until a period, t sv , to allow time to ensure that the bit transmission was stopped properly. the timings for data and break communi - cation are given in the serial communication timing specifi - cation and illustration sections. communication with the bq2011k is always performed with the least-significant bit being transmitted first. figure 3 shows an example of a communication se - quence to read the bq2011k nac register. bq2011k registers the bq2011k command and status registers are listed in table 5 and described below. command register (cmdr) the write-only cmdr register is accessed when eight valid command bits have been received by the bq2011k. the cmdr register contains two fields: w/r bit command address the w/r bit of the command register is used to select whether the received command is for a read or a write function. the w/r values are: where w/r is: 0 the bq2011k outputs the requested regis - ter contents specified by the address por - tion of cmdr. 1 the following eight bits should be written to the register specified by the address por - tion of cmdr. the lower seven-bit field of cmdr contains the address portion of the register to be accessed. attempts to write to invalid addresses are ignored. primary status flags register (flgs1) the read-only flgs1 register (address=01h) contains the primary bq2011k flags. 9 bq2011k td201103.eps dq break 0 0 0 0 0 0 1 0 1 0 0 1 written by host to bq2011k cmdr = 03h received by host to bq2011k nac = 65h lsb msb lsb msb 1 110 figure 3. typical communication with the bq2011k cmdr bits 765 4 3 2 1 0 - ad6 ad5 ad4 ad3 ad2 ad1 ad0 (lsb) cmdr bits 76543 2 1 0 w/r - -- - - - - 10 bq2011k symbol register name loc. (hex) read/ write control field 7(msb) 6 5 4321 0(lsb) cmdr command register 00h write w/r ad6 ad5 ad4 ad3 ad2 ad1 ad0 flgs1 primary status flags register 01h read chgs brp mcv n/u vdq n/u edv n/u tmpgg temperature and gas gauge register 02h read tmp3 tmp2 tmp1 tmp0 gg3 gg2 gg1 gg0 nach nominal available charge high byte register 03h r/w nach7 nach6 nach5 nach4 nach3 nach2 nach1 nach0 nacl nominal available charge low byte register 17h read nacl7 nacl6 nacl5 nacl4 nacl3 nacl2 nacl1 nacl0 batid battery identification register 04h r/w batid7 batid6 batid5 batid4 batid3 batid2 batid1 batid0 lmd last meas- ured dis- charge regis - ter 05h r/w lmd7 lmd6 lmd5 lmd4 lmd3 lmd2 lmd1 lmd0 flgs2 secondary status flags register 06h read cr dr2 dr1 dr0 n/u n/u n/u ovld octl output con - trol register 0ah write 1 oc5 oc4 oc3 oc2 oc1 n/u oce rst reset register 39h write rst 0 0 00000 note: n/u = not used table 5. bq2011k command and status registers the charge status flag (chgs) is asserted when a valid charge rate is detected. charge rate is deemed valid when v sro < -400 v. a v sro of greater than- 400 v or discharge activity clears chgs. the chgs values are: where chgs is: 0 either discharge activity detected or v sro > -400 v 1v sro < -400 v the battery replaced flag (brp) is asserted whenever the potential on the sb pin (relative to v ss ), v sb , rises above 0.1v and determines the internal registers have been corrupted. the brp flag is also set when the bq2011k is reset (see the rst register description). brp is cleared if either the bq2011k is charged until nac = lmd or discharged until edv is reached. brp = 1 signifies that the device has been reset. the brp values are: where brp is: 0 bq2011k is charged until nac = lmd or discharged until the edv flag is asserted 1 initial or full v cc reset, or a serial port ini - tiated reset has occurred the maximum cell voltage flag (mcv) is asserted whenever the potential on the sb pin (relative to v ss )is above 2.0v. the mcv flag is asserted until the condition causing mcv is removed. the mcv values are: where mcv is: 0v sb < 2.0v 1v sb > 2.0v the valid discharge flag (vdq) is asserted when the bq2011k is discharged from nac=lmd. the flag re - mains set until either lmd is updated or one of three actions that can clear vdq occurs: the self-discharge count register (sdcr) has exceeded the maximum acceptable value (4096 counts) for an lmd update. a valid charge action equal to 256 nac counts with v sro < -400 v. the edv flag was set at a temperature below 0c the vdq values are: where vdq is: 0 sdcr 4096, subsequent valid charge ac - tion detected, or edv is asserted with the temperature less than 0c 1 on first discharge after nac = lmd the end-of-discharge warning flag (edv) warns the user that the battery is empty. seg1 blinks at a 4hz rate. edv detection is disabled if ovld = 1. the edv flag is latched until a valid charge has been detected. the edv values are: where edv is: 0 valid charge action detected 1v sb < v edv temperature and gas gauge register (tmpgg) the read-only tmpgg register (address=02h) contains two data fields. the first field contains the battery tem - perature. the second field contains the available charge from the battery. the bq2011k contains an internal temperature sensor. the temperature is used to set charge efficiency factors as well as to adjust the self-discharge coefficient. the temperature register contents may be translated as shown in table 6. 11 bq2011k flgs1 bits 76543 2 1 0 - - mcv - - - - - flgs1 bits 76543 2 1 0 - brp - - - - - - flgs1 bits 76543 2 1 0 - - - - vdq - - - flgs1 bits 76543 2 1 0 chgs - -- - - - - tmpgg temperature bits 7 6 5 4 3210 tmp3 tmp2 tmp1 tmp0 - - - flgs1 bits 7654 3 2 1 0 ---- - -edv- the bq2011k calculates the available charge as a func- tion of nac, temperature, and a full reference, either lmd or pfc. the results of the calculation are avail- able via the display port or the gas gauge field of the tmpgg register. the register is used to give available capacity in 1 16 increments from 0 to 15 16 . the gas gauge display and the gas gauge portion of the tmpgg register are adjusted for cold temperature de - pendencies. a piece-wise correction is performed as fol - lows: the adjustment between > 0c and -20 c the fast charge regime efficiency factors are used when cr = 1. when cr = 0, the trickle charge efficiency fac - tors are used. the time to change cr varies due to the user-selectable count rates. the discharge rate flags, dr2?0, are bits 6?4. they are used to determine the present discharge re - gime as follows: the overload flag (ovld) is asserted when a discharge overload is detected, v sro > 60mv. ovld remains as- serted as long as the condition is valid. output control register (octl) the write-only octl register (address=0ah) provides the system with a means to check the display connections for the bq2011k. the segment drivers may be overwritten by data from octl when the least-significant bit of octl, oce, is set. the data in bits oc 5?1 of the octl register (see table 5 for details) is output onto the segment pins, seg 5?1 , respectively if oce=1. whenever oce is written to 1, the msb of octl should be set to a 1. the oce reg - ister location must be cleared to return the bq2011k to normal operation. oce may be cleared by either writing the bit to a logic zero via the serial port or by resetting the bq2011k as explained below. note: whenever the octl register is written, the msb of octl should be written to a logic one. reset register (rst) the reset register (address=39h) provides the means to perform a software-controlled reset of the device. a full device reset may be accomplished by first writing lmd (address = 05h) to 00h and then writing the rst regis - ter contents from 00h to 80h. setting any bit other than the most-significant bit of the rst register is not al - lowed , and results in improper operation of the bq2011k. resetting the bq2011k sets the following: lmd = pfc vdq, oce, and nac = 0 (nac = pfc when prog 4 = l) brp = 1 display the bq2011k can directly display capacity information using low-power leds. if leds are used, the segment pins should be tied to v cc , the battery, or the lcom pin through resistors for programming the bq2011k. the bq2011k displays the battery charge state in abso- lute mode. in absolute mode, each segment represents a fixed amount of charge, based on the initial pfc. in ab- solute mode, each segment represents 20% of the pfc. as the battery wears out over time, it is possible for the lmd to be below the initial pfc. in this case, all of the leds may not turn on, representing the reduction in the actual battery capacity. the capacity display is also adjusted for the present bat - tery temperature. the temperature adjustment reflects the available capacity at a given temperature but does not affect the nac register. the temperature adjustments are detailed in the tmpgg register description. when disp is tied to v cc , the seg 1?5 outputs are inac - tive. when disp is left floating, the display becomes ac - tive during charge if the nac registers are counting at a rate equivalent to v sro < -2mv or fast discharge if the nac registers are counting at a rate equivalent to v sro > 2mv. when disp is left floating, the display also be - comes active after the detection of a discharge signal with a minimum amplitude of v sr > 20mv (10a for r s = 0.002 ? ) and a minimum pulse width of 25ms. when disp is pulled low, the segment outputs become active for 4s, 0.5s. 13 bq2011k flgs2 bits 7 6 5 4 3210 - dr2 dr1 dr0 - - - dr2 dr1 dr0 v sro (mv) 000 010 < v sro 001 10 20 < v sro 010 20 40 < v sro 011 40 60 < v sro 100 v sro > 60 flgs2 bits 76543 2 1 0 - - - - - - - ovld the segment outputs are modulated as two banks, with segments 1, 3, and 5 alternating with segments 2 and 4. the segment outputs are modulated at approximately 320hz, with each bank active for 30% of the period. seg 1 blinks at a 4hz rate whenever v sb has been de - tected to be below v edv to indicate a low-battery condi - tion or nac is less than 10% of pfc. microregulator the bq2011k can operate directly from 4 cells. to facili - tate the power supply requirements of the bq2011k, an ref output is provided to regulate an external low- threshold n-fet. a micropower source for the bq2011k can be inexpensively built using the fet and an exter - nal resistor. 14 bq2011k 15 bq2011k absolute maximum ratings symbol parameter minimum maximum unit notes v cc relative to v ss -0.3 7.0 v all other pins relative to v ss -0.3 7.0 v v sr relative to v ss -0.3 7.0 v minimum 100 ? series resistor should be used to protect sr in case of a shorted battery (see the bq2011k application note for details). t opr operating temperature 0 70 c commercial -40 85 c industrial note: permanent device damage may occur if absolute maximum ratings are exceeded. functional opera - tion should be limited to the recommended dc operating conditions detailed in this data sheet. expo- sure to conditions beyond the operational limits for extended periods of time may affect device reliability. dc voltage thresholds (t a = t opr ; v = 3.0 to 6.5v) symbol parameter minimum typical maximum unit notes v edv end-of-discharge warning 0.96 ? v edv v edv 1.04 ? v edv vsb v srq valid charge - - -400 v v sr + v os v srd valid discharge 500 - - v v sr + v os v mcv maximum single-cell voltage 1.95 2.0 2.05 v sb note: for proper operation of the threshold detection circuit, v cc must be at least 1.5v greater than the volt - age being measured. 16 bq2011k dc electrical characteristics (t a = t opr ) symbol parameter minimum typical maximum unit notes v cc supply voltage 3.0 4.25 6.5 v v cc excursion from < 2.0v to 3.0v initializes the unit. vos offset referred to v sr - 50 150 v disp = v cc v ref reference at 25c 5.7 6.0 6.3 v i ref = 5 a reference at -40c to +85c 4.5 - 7.5 v i ref = 5 a r ref reference input impedance 2.0 5.0 - m ? v ref = 3v i cc normal operation - 90 135 a v cc = 3.0v, dq = 0 - 120 180 a v cc = 4.25v, dq = 0 - 170 250 a v cc = 6.5v, dq = 0 v sb battery input 0 - v cc v r sbmax sb input impedance 10 - - m ? 0 < v sb < v cc i disp disp input leakage - - 5 a v disp = v ss i lcom lcom input leakage -0.2 - 0.2 a disp = v cc i rbi rbi data-retention current - - 100 na v rbi > v cc < 3v r dq internal pulldown 500 - - k ? v sr sense resistor input -0.3 - 2.0 v v sr >v ss = discharge; v sr < v ss = charge r sr sr input impedance 10 - - m ? -200mv < v sr < v cc v ihpfc prog/spfc logic input high v cc - 0.2 - - v spfc, prog 1-4 v ilpfc prog/spfc logic input low - - v ss + 0.2 v spfc, prog 1-4 v izpfc prog/spfc logic input z float - float v spfc, prog 1-4 i ihpfc prog/spfc input high cur- rent - 1.2 - a v pfc = v cc /2 i ilpfc prog/spfc input low current - 1.2 - av pfc = v cc /2 v olsl seg x output low, low v cc - 0.1 - v v cc = 3v, i ols 1.75ma seg 1 ?seg 5 v olsh seg x output low, high v cc - 0.4 - v v cc = 6.5v, i ols 11.0ma seg 1 ?seg 5 v ohml lcom output high, low v cc v cc - 0.3 - - v v cc = 3v, i ohlcom = -5.25ma v ohmh lcom output high, high v cc v cc - 0.6 - - v v cc = 6.5v, i ohlcom = -33.0ma i ohlcom lcom source current -33 - - ma at v ohlcom = v cc - 0.6v i ols seg x sink current 11.0 - - ma at v olsh = 0.4v, v cc = 6.5v i ol open-drain sink current 5.0 - - ma at v ol = v ss + 0.3v, dq v ol open-drain output low - - 0.5 v i ol 5ma, dq v ihdq dq input high 2.5 - - v dq v ildq dq input low - - 0.8 v dq r float float state external impedance - 5 - m ? spfc, prog 1-4 note: all voltages relative to v ss . 17 bq2011k serial communication timing specification (t a =t opr ) symbol parameter minimum typical maximum unit notes t cych cycle time, host to bq2011k 3 - - ms see note t cycb cycle time, bq2011k to host 3 - 6 ms t strh start hold, host to bq2011k 5 - - ns t strb start hold, bq2011k to host 500 - - s t dsu data setup - - 750 s t dh data hold 750 - - s t dv data valid 1.50 - - ms t ssu stop setup - - 2.25 ms t sh stop hold 700 - - s t sv stop valid 2.95 - - ms t b break 3 - - ms t br break recovery 1 - - ms note: the open-drain dq pin should be pulled to at least v cc by the host system for proper dq operation. dq may be left floating if the serial interface is not used. td201002.eps dq (r/w "1") t strh t strb t dsu t dh t dv t sv t ssu t sh t cych, t cycb, t b t br dq (r/w "0") dq (break) serial communication timing illustration 18 bq2011k 16-pin soic narrow (sn) 16-pin sn ( soic narrow ) dimension minimum maximum a 0.060 0.070 a1 0.004 0.010 b 0.013 0.020 c 0.007 0.010 d 0.385 0.400 e 0.150 0.160 e 0.045 0.055 h 0.225 0.245 l 0.015 0.035 all dimensions are in inches. a a1 .004 c b e d e h l 19 bq2011k * contact factory for availability. ordering information bq2011k package option: sn = 16-pin narrow soic device: bq2011k gas gauge ic temperature range: blank = commercial (0 to +70c) n = industrial (-40 to +85c)* data sheet revision history change no. page no. description nature of change 1 6 removed relative display mode from table 1 correction notes: change 1 = oct. 1997 b changes from oct. 1995. important notice texas instruments and its subsidiaries (ti) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. ti warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with ti's standard warranty. testing and other quality control techniques are utilized to the extent ti deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage (acritical applicationso). ti semiconductor products are not designed, authorized, or warranted to be suitable for use in life-support devices or systems or other critical applications. inclusion of ti products in such applications is understood to be fully at the customer's risk. in order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. ti assumes no liability for applications assistance or customer product design. ti does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of ti covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. ti's publication of information regarding any third party's products or services does not constitute ti's approval, warranty or endorsement thereof. copyright ? 1999, texas instruments incorporated |
Price & Availability of BQ2011KSN-N
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |